sycl: *glu flat path (llama/26354)
* tests: add SWIGLU perf cases perf mode had no GLU coverage. Adds SWIGLU at 17408 columns, 512 and 2048 tokens, f16 and f32, with the operands both fused and split. * sycl: consolidate fused-GLU kernels They differed only in which op_* they called, so take the op as an argument and share a common launcher. Their block sizes were all 256, so launch geometry is unchanged; SYCL_GELU_BLOCK_SIZE and SYCL_SILU_BLOCK_SIZE lose their last users so are dropped. * sycl: contiguous fast path for the fused GLU ops o0 == n and o1 == n collapse the de-interleave index math to the identity, so dispatch a flat kernel in that case. It fires for ggml_glu_split with packed operands; a fused [gate|up] tensor keeps the strided path. test-backend-ops perf -o SWIGLU on an Arc Pro B70: split +14% f16 and +4% f32, fused unchanged.
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9faa9ee7b0
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077c5d42d2
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@ -420,53 +420,31 @@ static void clamp(const T * x, T * dst, const float min, const float max, const
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}
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}
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template<typename T>
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static void gated_op_fused_geglu(const T * x, const T * g, T * dst, const uint64_t k, const sycl::uint3 n_fd, const uint64_t o0, const uint64_t o1, const sycl::nd_item<1> &item_ct1) {
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template<typename T, typename F>
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static void unary_gated_op_flat_kernel(const T * x, const T * g, T * dst, const uint64_t k, const sycl::nd_item<1> & item_ct1, F func) {
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SYCL_GLOBAL_ID_LOOP(k, item_ct1) {
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dst[i] = func(x[i]) * g[i];
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}
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}
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template<typename T, typename F>
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static void unary_gated_op_generic_kernel(
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const T * x,
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const T * g,
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T * dst,
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const uint64_t k,
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const sycl::uint3 n_fd,
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const uint64_t o0,
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const uint64_t o1,
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const sycl::nd_item<1> & item_ct1,
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F func) {
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// rows of n columns at strides o0 and o1: two halves of one fused tensor, or two tensors
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SYCL_GLOBAL_ID_LOOP(k, item_ct1) {
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const sycl::uint2 rc = fast_div_modulo((uint32_t) i, n_fd);
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const int64_t j0 = rc.x() * o0 + rc.y();
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const int64_t j1 = o0 == o1 ? j0 : rc.x() * o1 + rc.y();
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dst[i] = op_gelu(x[j0]) * g[j1];
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}
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}
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template<typename T>
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static void gated_op_fused_reglu(const T * x, const T * g, T * dst, const uint64_t k, const sycl::uint3 n_fd, const uint64_t o0, const uint64_t o1, const sycl::nd_item<1> &item_ct1) {
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SYCL_GLOBAL_ID_LOOP(k, item_ct1) {
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const sycl::uint2 rc = fast_div_modulo((uint32_t) i, n_fd);
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const int64_t j0 = rc.x() * o0 + rc.y();
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const int64_t j1 = o0 == o1 ? j0 : rc.x() * o1 + rc.y();
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dst[i] = op_relu(x[j0]) * g[j1];
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}
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}
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template<typename T>
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static void gated_op_fused_swiglu(const T * x, const T * g, T * dst, const uint64_t k, const sycl::uint3 n_fd, const uint64_t o0, const uint64_t o1, const sycl::nd_item<1> &item_ct1) {
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SYCL_GLOBAL_ID_LOOP(k, item_ct1) {
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const sycl::uint2 rc = fast_div_modulo((uint32_t) i, n_fd);
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const int64_t j0 = rc.x() * o0 + rc.y();
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const int64_t j1 = o0 == o1 ? j0 : rc.x() * o1 + rc.y();
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dst[i] = op_silu(x[j0]) * g[j1];
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}
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}
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template<typename T>
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static void gated_op_fused_geglu_erf(const T * x, const T * g, T * dst, const uint64_t k, const sycl::uint3 n_fd, const uint64_t o0, const uint64_t o1, const sycl::nd_item<1> &item_ct1) {
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SYCL_GLOBAL_ID_LOOP(k, item_ct1) {
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const sycl::uint2 rc = fast_div_modulo((uint32_t) i, n_fd);
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const int64_t j0 = rc.x() * o0 + rc.y();
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const int64_t j1 = o0 == o1 ? j0 : rc.x() * o1 + rc.y();
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dst[i] = op_gelu_erf(x[j0]) * g[j1];
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}
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}
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template<typename T>
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static void gated_op_fused_geglu_quick(const T * x, const T * g, T * dst, const uint64_t k, const sycl::uint3 n_fd, const uint64_t o0, const uint64_t o1, const sycl::nd_item<1> &item_ct1) {
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SYCL_GLOBAL_ID_LOOP(k, item_ct1) {
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const sycl::uint2 rc = fast_div_modulo((uint32_t) i, n_fd);
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const int64_t j0 = rc.x() * o0 + rc.y();
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const int64_t j1 = o0 == o1 ? j0 : rc.x() * o1 + rc.y();
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dst[i] = op_gelu_quick(x[j0]) * g[j1];
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dst[i] = func(x[j0]) * g[j1];
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}
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}
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@ -670,6 +648,35 @@ static inline void ggml_sycl_op_unary(
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});
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}
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template<typename F>
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static inline void ggml_sycl_op_unary_gated(
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ggml_backend_sycl_context & ctx, ggml_tensor * dst, F func) {
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dispatch_ggml_sycl_op_fused_glu(ctx, dst,
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[func](const auto * x_ptr, const auto * g_ptr, auto * dst_ptr, uint64_t k, uint64_t n, uint64_t o0, uint64_t o1, queue_ptr main_stream) {
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const uint32_t num_blocks = (uint32_t) ceil_div(k, SYCL_GLU_BLOCK_SIZE);
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const sycl::nd_range<1> launch_range(num_blocks * sycl::range<1>(SYCL_GLU_BLOCK_SIZE),
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sycl::range<1>(SYCL_GLU_BLOCK_SIZE));
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// o0 == n and o1 == n make the index math the identity, so index flat
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// note: not ggml_is_contiguous - a fused [gate|up] src0 is contiguous with o0 == 2n
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if (o0 == n && o1 == n) {
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main_stream->parallel_for(launch_range,
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[=](sycl::nd_item<1> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] {
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unary_gated_op_flat_kernel(x_ptr, g_ptr, dst_ptr, k, item_ct1, func);
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});
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} else {
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// launch-invariant divisor, and only this path needs it
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const sycl::uint3 n_fd = init_fastdiv_values((uint32_t) n);
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main_stream->parallel_for(launch_range,
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[=](sycl::nd_item<1> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] {
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unary_gated_op_generic_kernel(x_ptr, g_ptr, dst_ptr, k, n_fd, o0, o1, item_ct1, func);
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});
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}
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});
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}
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static inline void ggml_sycl_op_arange(ggml_backend_sycl_context & ctx, ggml_tensor * dst) {
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GGML_ASSERT(dst->type == GGML_TYPE_F32);
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@ -967,42 +974,21 @@ static inline void ggml_sycl_op_acc(ggml_backend_sycl_context & ctx, ggml_tensor
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}
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static inline void ggml_sycl_op_geglu(ggml_backend_sycl_context & ctx, ggml_tensor * dst) {
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ggml_sycl_detail::dispatch_ggml_sycl_op_fused_glu(ctx, dst,
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[](const auto* x_ptr, const auto* g_ptr, auto* dst_ptr, uint64_t k, uint64_t n, uint64_t o0, uint64_t o1, queue_ptr main_stream) {
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const uint32_t num_blocks = ceil_div(k, SYCL_GELU_BLOCK_SIZE);
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const sycl::uint3 n_fd = init_fastdiv_values((uint32_t) n);
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main_stream->parallel_for(
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sycl::nd_range<1>((num_blocks * sycl::range<1>(SYCL_GELU_BLOCK_SIZE)),
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sycl::range<1>(SYCL_GELU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] {
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gated_op_fused_geglu(x_ptr, g_ptr, dst_ptr, k, n_fd, o0, o1, item_ct1);
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});
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});
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ggml_sycl_detail::ggml_sycl_op_unary_gated(ctx, dst, [](auto x) {
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return op_gelu(x);
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});
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}
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static inline void ggml_sycl_op_reglu(ggml_backend_sycl_context & ctx, ggml_tensor * dst) {
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ggml_sycl_detail::dispatch_ggml_sycl_op_fused_glu(ctx, dst,
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[](const auto* x_ptr, const auto* g_ptr, auto* dst_ptr, uint64_t k, uint64_t n, uint64_t o0, uint64_t o1, queue_ptr main_stream) {
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const uint32_t num_blocks = ceil_div((uint32_t)k, SYCL_RELU_BLOCK_SIZE); // Using RELU block size for reglu
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const sycl::uint3 n_fd = init_fastdiv_values((uint32_t) n);
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main_stream->parallel_for(
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sycl::nd_range<1>((num_blocks * sycl::range<1>(SYCL_RELU_BLOCK_SIZE)),
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sycl::range<1>(SYCL_RELU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] {
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gated_op_fused_reglu(x_ptr, g_ptr, dst_ptr, k, n_fd, o0, o1, item_ct1);
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});
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});
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ggml_sycl_detail::ggml_sycl_op_unary_gated(ctx, dst, [](auto x) {
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return op_relu(x);
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});
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}
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static inline void ggml_sycl_op_swiglu(ggml_backend_sycl_context & ctx, ggml_tensor * dst) {
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ggml_sycl_detail::dispatch_ggml_sycl_op_fused_glu(ctx, dst,
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[](const auto* x_ptr, const auto* g_ptr, auto* dst_ptr, uint64_t k, uint64_t n, uint64_t o0, uint64_t o1, queue_ptr main_stream) {
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const uint32_t num_blocks = ceil_div((uint32_t)k, SYCL_SILU_BLOCK_SIZE); // Using SILU block size for swiglu
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const sycl::uint3 n_fd = init_fastdiv_values((uint32_t) n);
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main_stream->parallel_for(
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sycl::nd_range<1>((num_blocks * sycl::range<1>(SYCL_SILU_BLOCK_SIZE)),
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sycl::range<1>(SYCL_SILU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] {
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gated_op_fused_swiglu(x_ptr, g_ptr, dst_ptr, k, n_fd, o0, o1, item_ct1);
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});
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});
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ggml_sycl_detail::ggml_sycl_op_unary_gated(ctx, dst, [](auto x) {
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return op_silu(x);
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});
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}
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__dpct_inline__ float ggml_sycl_op_swiglu_oai_single(float x, float g, float alpha = 1.702f, float limit = 7.0f) {
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@ -1097,29 +1083,15 @@ void ggml_sycl_op_swiglu_oai(ggml_backend_sycl_context & ctx, ggml_tensor * dst)
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}
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static inline void ggml_sycl_op_geglu_erf(ggml_backend_sycl_context & ctx, ggml_tensor * dst) {
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ggml_sycl_detail::dispatch_ggml_sycl_op_fused_glu(ctx, dst,
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[](const auto* x_ptr, const auto* g_ptr, auto* dst_ptr, uint64_t k, uint64_t n, uint64_t o0, uint64_t o1, queue_ptr main_stream) {
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const uint32_t num_blocks = ceil_div(k, SYCL_GELU_BLOCK_SIZE);
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const sycl::uint3 n_fd = init_fastdiv_values((uint32_t) n);
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main_stream->parallel_for(
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sycl::nd_range<1>((num_blocks * sycl::range<1>(SYCL_GELU_BLOCK_SIZE)),
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sycl::range<1>(SYCL_GELU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] {
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gated_op_fused_geglu_erf(x_ptr, g_ptr, dst_ptr, k, n_fd, o0, o1, item_ct1);
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});
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});
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ggml_sycl_detail::ggml_sycl_op_unary_gated(ctx, dst, [](auto x) {
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return op_gelu_erf(x);
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});
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}
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static inline void ggml_sycl_op_geglu_quick(ggml_backend_sycl_context & ctx, ggml_tensor * dst) {
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ggml_sycl_detail::dispatch_ggml_sycl_op_fused_glu(ctx, dst,
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[](const auto* x_ptr, const auto* g_ptr, auto* dst_ptr, uint64_t k, uint64_t n, uint64_t o0, uint64_t o1, queue_ptr main_stream) {
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const uint32_t num_blocks = ceil_div(k, SYCL_GELU_BLOCK_SIZE);
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const sycl::uint3 n_fd = init_fastdiv_values((uint32_t) n);
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main_stream->parallel_for(
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sycl::nd_range<1>((num_blocks * sycl::range<1>(SYCL_GELU_BLOCK_SIZE)),
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sycl::range<1>(SYCL_GELU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] {
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gated_op_fused_geglu_quick(x_ptr, g_ptr, dst_ptr, k, n_fd, o0, o1, item_ct1);
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});
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});
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ggml_sycl_detail::ggml_sycl_op_unary_gated(ctx, dst, [](auto x) {
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return op_gelu_quick(x);
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});
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}
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@ -20,8 +20,6 @@
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#define MATRIX_ROW_PADDING 512 // last row of quant. matrices is a multiple of this to avoid out-of-bounds memory accesses
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#define SYCL_COL2IM_1D_BLOCK_SIZE 256
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#define SYCL_GELU_BLOCK_SIZE 256
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#define SYCL_SILU_BLOCK_SIZE 256
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#define SYCL_TANH_BLOCK_SIZE 256
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#define SYCL_RELU_BLOCK_SIZE 256
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#define SYCL_HARDSIGMOID_BLOCK_SIZE 256
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