0d3bdb76ec
CPUID feature bits report hardware capability only. The OS must also have enabled the relevant extended register state in XCR0 before VEX/ EVEX instructions can execute safely. Without this check, a process on a hypervisor or restricted OS that has not set XCR0[2:1]/[7:5]/ [18:17] will receive SIGILL the moment it hits an AVX/AVX-512/AMX instruction — even though CPUID reports support. Add three helpers to cpuid_x86: os_saves_ymm() — OSXSAVE + XCR0[2:1] (AVX, AVX2, FMA, F16C, AVX-VNNI) os_saves_zmm() — chains os_saves_ymm() + XCR0[7:5] (all AVX-512) os_saves_amx() — chains os_saves_zmm() + XCR0[18:17] (AMX-INT8) xgetbv() is portable: _xgetbv() on MSVC, inline asm on GCC/Clang. Resolves the long-standing FIXME comment in ggml_backend_cpu_x86_score(). |
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| cmake | ||
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| .gitignore | ||
| CMakeLists.txt | ||