ggml : require contiguous src for ROLL on CUDA and Metal (llama/25928)
ggml_roll only asserts nb[0] == ggml_type_size, so a permuted src is a valid input, but the CUDA and Metal roll kernels index by ne alone and never read the nb strides. A non-contiguous src therefore produced silently wrong results. Neither backend declared a contiguity requirement in supports_op, so the scheduler did not fall back to the CPU implementation, which does handle strides correctly. Add the requirement to both backends, matching the existing GGML_OP_ROPE guard, and add a permuted test_roll case.
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@ -5185,7 +5185,7 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g
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return max_bias == 0.0f;
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return max_bias == 0.0f;
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}
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}
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case GGML_OP_ROLL:
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case GGML_OP_ROLL:
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if(op->src[0]->type == GGML_TYPE_F32) {
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if(op->src[0]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0])) {
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return true;
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return true;
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}
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}
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return false;
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return false;
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@ -1268,8 +1268,9 @@ bool ggml_metal_device_supports_op(ggml_metal_device_t dev, const struct ggml_te
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case GGML_OP_ARGSORT:
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case GGML_OP_ARGSORT:
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case GGML_OP_TOP_K:
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case GGML_OP_TOP_K:
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case GGML_OP_ARANGE:
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case GGML_OP_ARANGE:
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case GGML_OP_ROLL:
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return true;
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return true;
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case GGML_OP_ROLL:
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return ggml_is_contiguous(op->src[0]);
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case GGML_OP_FLASH_ATTN_EXT:
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case GGML_OP_FLASH_ATTN_EXT:
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// for new head sizes, add checks here
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// for new head sizes, add checks here
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if (op->src[0]->ne[0] != 32 &&
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if (op->src[0]->ne[0] != 32 &&
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