cuda : extend GGML_OP_PAD to work with non-cont src0 (llama/19429)
* cuda : extend GGML_OP_PAD to work with non-cont src0 * tests : add permuted pad
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@ -7629,8 +7629,7 @@ static void ggml_compute_forward_pad_f32(
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const ggml_tensor * src0 = dst->src[0];
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GGML_ASSERT(src0->nb[0] == sizeof(float));
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GGML_ASSERT( dst->nb[0] == sizeof(float));
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assert(dst->nb[0] == sizeof(float));
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const int ith = params->ith;
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const int nth = params->nth;
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@ -4834,8 +4834,9 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g
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case GGML_OP_SUM_ROWS:
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case GGML_OP_MEAN:
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case GGML_OP_GROUP_NORM:
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case GGML_OP_PAD:
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return ggml_is_contiguous(op->src[0]);
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case GGML_OP_PAD:
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return true;
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case GGML_OP_UPSCALE:
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case GGML_OP_PAD_REFLECT_1D:
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case GGML_OP_ARANGE:
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@ -7,7 +7,7 @@ __device__ __forceinline__ int64_t wrap_around(int64_t coord, int64_t size) {
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return (coord + size) % size;
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}
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static __global__ void pad_f32(const float * src, float * dst,
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static __global__ void pad_f32(const float * src, size_t s00, size_t s01, size_t s02, size_t s03, float * dst,
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const int lp0, const int rp0, const int lp1, const int rp1,
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const int lp2, const int rp2, const int lp3, const int rp3,
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const int ne0, const int ne1, const int ne2, const int ne3,
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@ -34,11 +34,8 @@ static __global__ void pad_f32(const float * src, float * dst,
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const int64_t i01 = i1 - lp1;
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const int64_t i02 = i2 - lp2;
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const int64_t i03 = i3 - lp3;
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const int64_t ne02 = ne2 - lp2 - rp2;
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const int64_t ne01 = ne1 - lp1 - rp1;
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const int64_t ne00 = ne0 - lp0 - rp0;
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const int64_t src_idx = i03 * (ne00 * ne01 * ne02) + i02 * (ne00 * ne01) + i01 * ne00 + i00;
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const int64_t src_idx = i03 * s03 + i02 * s02 + i01 * s01 + i00 * s00;
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dst[dst_idx] = src[src_idx];
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} else {
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@ -57,21 +54,21 @@ static __global__ void pad_f32(const float * src, float * dst,
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const int64_t i02 = wrap_around(i2 - lp2, ne02);
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const int64_t i03 = wrap_around(i3 - lp3, ne03);
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const int64_t src_idx = i03 * (ne00 * ne01 * ne02) + i02 * (ne00 * ne01) + i01 * ne00 + i00;
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const int64_t src_idx = i03 * s03 + i02 * s02 + i01 * s01 + i00 * s00;
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dst[dst_idx] = src[src_idx];
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}
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}
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static void pad_f32_cuda(const float * src, float * dst,
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static void pad_f32_cuda(const float * src, size_t s00, size_t s01, size_t s02, size_t s03, float * dst,
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const int lp0, const int rp0, const int lp1, const int rp1,
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const int lp2, const int rp2, const int lp3, const int rp3,
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const int ne0, const int ne1, const int ne2, const int ne3,
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const bool circular, cudaStream_t stream) {
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int num_blocks = (ne0 + CUDA_PAD_BLOCK_SIZE - 1) / CUDA_PAD_BLOCK_SIZE;
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dim3 gridDim(num_blocks, ne1, ne2 * ne3);
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pad_f32<<<gridDim, CUDA_PAD_BLOCK_SIZE, 0, stream>>>(src, dst,
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pad_f32<<<gridDim, CUDA_PAD_BLOCK_SIZE, 0, stream>>>(src, s00, s01, s02, s03, dst,
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lp0, rp0, lp1, rp1, lp2, rp2, lp3, rp3,
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ne0, ne1, ne2, ne3, circular);
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}
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@ -82,9 +79,10 @@ void ggml_cuda_op_pad(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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float * dst_d = (float *) dst->data;
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cudaStream_t stream = ctx.stream();
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GGML_TENSOR_UNARY_OP_LOCALS;
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GGML_ASSERT(src0->type == GGML_TYPE_F32);
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GGML_ASSERT(dst->type == GGML_TYPE_F32);
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GGML_ASSERT(ggml_is_contiguous(src0));
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const int32_t lp0 = ((const int32_t *) (dst->op_params))[0];
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const int32_t rp0 = ((const int32_t *) (dst->op_params))[1];
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@ -96,7 +94,12 @@ void ggml_cuda_op_pad(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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const int32_t rp3 = ((const int32_t *) (dst->op_params))[7];
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const int32_t circular = ((const int32_t *) (dst->op_params))[8];
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pad_f32_cuda(src0_d, dst_d,
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const size_t s00 = nb00 / ggml_type_size(src0->type);
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const size_t s01 = nb01 / ggml_type_size(src0->type);
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const size_t s02 = nb02 / ggml_type_size(src0->type);
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const size_t s03 = nb03 / ggml_type_size(src0->type);
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pad_f32_cuda(src0_d, s00, s01, s02, s03, dst_d,
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lp0, rp0, lp1, rp1, lp2, rp2, lp3, rp3,
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dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3],
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(bool) circular, stream);
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