Optimize Q4_0 mul_mat for Arc770, add scripts (llama/22291)
* opt arc770 for Q4_0 * add for Q4_0 * update the script * add help script for windows * update guide * fix format issue * convert from dos to unix for format issue * fix missed -sm parameter
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@ -224,7 +224,7 @@ struct sycl_device_info {
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// cudaOccupancyMaxActiveBlocksPerMultiprocessor
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bool vmm; // virtual memory support
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size_t total_vram;
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//sycl_hw_info hw_info; \\ device id and aarch, currently not used
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sycl_hw_info hw_info;
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optimize_feature opt_feature;
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};
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@ -104,6 +104,7 @@ static ggml_sycl_device_info ggml_sycl_init() {
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info.max_work_group_sizes[i] = prop.get_max_work_group_size();
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info.devices[i].max_wg_per_cu = info.max_work_group_sizes[i] / prop.get_max_compute_units();
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info.devices[i].hw_info = get_device_hw_info(&device);
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}
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@ -3703,9 +3704,16 @@ static void ggml_sycl_mul_mat(ggml_backend_sycl_context & ctx, const ggml_tensor
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// Dispatch becomes obscure with the reorder, MMVQ when the reorder optimization
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// is enabled takes precedence over DMMV, the current if-else implementation
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// requires disabling DMMV if both conditions are met
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if (!g_ggml_sycl_prioritize_dmmv && ((should_reorder_tensor(ctx, dst) &&
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ggml_sycl_supports_reorder_mmvq(src0->type)))) {
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use_dequantize_mul_mat_vec = use_dequantize_mul_mat_vec && !use_mul_mat_vec_q;
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// Arc770 get benefit with Q4_0 by skipping it.
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if (!(ggml_sycl_info().devices[ctx.device].hw_info.arch ==
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gpu_arch::intel_gpu_acm_g10 &&
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src0->type == GGML_TYPE_Q4_0)) {
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use_dequantize_mul_mat_vec =
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use_dequantize_mul_mat_vec && !use_mul_mat_vec_q;
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}
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}
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if (!split && src0->type == GGML_TYPE_F16 && ggml_is_permuted(src0) && ggml_is_permuted(src1) && src1->ne[1] == 1) {
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@ -1,15 +1,67 @@
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#include "sycl_hw.hpp"
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// TODO: currently not used
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/*
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sycl_hw_info get_device_hw_info(sycl::device *device_ptr) {
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sycl_hw_info res;
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int32_t id = device_ptr->get_info<sycl::ext::intel::info::device::device_id>();
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res.device_id = id;
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using namespace std;
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syclex::architecture arch = device_ptr->get_info<syclex::info::device::architecture>();
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res.arch = arch;
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return res;
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}
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/*defined in
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* /opt/intel/oneapi/compiler/latest/include/sycl/ext/oneapi/experimental/device_architecture.def
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*/
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static map<gpu_arch, std::pair<const char*, sycl_intel_gpu_family>> arch2name = {
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{gpu_arch::intel_gpu_bdw, {"intel_gpu_bdw", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_skl, {"intel_gpu_skl", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_kbl, {"intel_gpu_kbl", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_cfl, {"intel_gpu_cfl", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_apl, {"intel_gpu_apl", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_glk, {"intel_gpu_glk", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_whl, {"intel_gpu_whl", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_aml, {"intel_gpu_aml", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_cml, {"intel_gpu_cml", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_icllp, {"intel_gpu_icllp", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_ehl, {"intel_gpu_ehl", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_tgllp, {"intel_gpu_tgllp", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_rkl, {"intel_gpu_rkl", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_adl_s, {"intel_gpu_adl_s", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_adl_p, {"intel_gpu_adl_p", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_adl_n, {"intel_gpu_adl_n", GPU_FAMILY_IGPU_NON_XE}},
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{gpu_arch::intel_gpu_dg1, {"intel_gpu_dg1", GPU_FAMILY_DGPU_CLIENT_GAME}},
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{gpu_arch::intel_gpu_acm_g10, {"intel_gpu_acm_g10", GPU_FAMILY_DGPU_CLIENT_GAME}},
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{gpu_arch::intel_gpu_acm_g11, {"intel_gpu_acm_g11", GPU_FAMILY_DGPU_CLIENT_GAME}},
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{gpu_arch::intel_gpu_acm_g12, {"intel_gpu_acm_g12", GPU_FAMILY_DGPU_CLIENT_GAME}},
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{gpu_arch::intel_gpu_pvc, {"intel_gpu_pvc", GPU_FAMILY_DGPU_CLOUD}},
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{gpu_arch::intel_gpu_pvc_vg, {"intel_gpu_pvc_vg", GPU_FAMILY_DGPU_CLOUD}},
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{gpu_arch::intel_gpu_mtl_u, {"intel_gpu_mtl_u", GPU_FAMILY_IGPU_XE}},
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{gpu_arch::intel_gpu_mtl_h, {"intel_gpu_mtl_h", GPU_FAMILY_IGPU_XE}},
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{gpu_arch::intel_gpu_arl_h, {"intel_gpu_arl_h", GPU_FAMILY_IGPU_XE}},
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{gpu_arch::intel_gpu_bmg_g21, {"intel_gpu_bmg_g21", GPU_FAMILY_DGPU_CLIENT_GAME}},
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{gpu_arch::intel_gpu_bmg_g31, {"intel_gpu_bmg_g31", GPU_FAMILY_DGPU_CLIENT_GAME}},
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{gpu_arch::intel_gpu_lnl_m, {"intel_gpu_lnl_m", GPU_FAMILY_IGPU_XE}},
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{gpu_arch::intel_gpu_ptl_h, {"intel_gpu_ptl_h", GPU_FAMILY_IGPU_XE}},
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{gpu_arch::intel_gpu_ptl_u, {"intel_gpu_ptl_u", GPU_FAMILY_IGPU_XE}},
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{gpu_arch::intel_gpu_wcl, {"intel_gpu_wcl", GPU_FAMILY_IGPU_XE}}
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};
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sycl_hw_info get_device_hw_info(sycl::device* device_ptr) {
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sycl_hw_info res;
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int32_t id =
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device_ptr->get_info<sycl::ext::intel::info::device::device_id>();
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res.device_id = id;
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res.name = device_ptr->get_info<sycl::info::device::name>();
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syclex::architecture arch =
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device_ptr->get_info<syclex::info::device::architecture>();
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res.arch = arch;
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map<syclex::architecture,
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std::pair<const char*, sycl_intel_gpu_family>>::iterator it =
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arch2name.find(res.arch);
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if (it != arch2name.end()) {
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res.arch_name = it->second.first;
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res.gpu_family = it->second.second;
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} else {
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res.arch_name = "unknown";
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res.gpu_family = GPU_FAMILY_UKNOWN;
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}
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return res;
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}
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@ -9,18 +9,30 @@
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#include <sycl/sycl.hpp>
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namespace syclex = sycl::ext::oneapi::experimental;
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using gpu_arch = sycl::ext::oneapi::experimental::architecture;
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// TODO: currently not used
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/*
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struct sycl_hw_info {
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syclex::architecture arch;
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int32_t device_id;
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// It's used to mark the GPU computing capacity
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// The value must flow the order of performance.
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enum sycl_intel_gpu_family {
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GPU_FAMILY_UKNOWN = -1,
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// iGPU without Xe core, before Meteor Lake iGPU(Xe)
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GPU_FAMILY_IGPU_NON_XE = 0,
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// iGPU with Xe core, Meteor Lake iGPU or newer.
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GPU_FAMILY_IGPU_XE = 1,
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// dGPU for gaming in client/data center (DG1/FLex 140 or newer).
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GPU_FAMILY_DGPU_CLIENT_GAME = 2,
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// dGPU for AI in cloud, PVC or newer.
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GPU_FAMILY_DGPU_CLOUD = 3
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};
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bool is_in_vector(std::vector<int> &vec, int item);
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struct sycl_hw_info {
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syclex::architecture arch;
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const char* arch_name;
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int32_t device_id;
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std::string name;
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sycl_intel_gpu_family gpu_family;
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};
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sycl_hw_info get_device_hw_info(sycl::device *device_ptr);
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*/
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#endif // SYCL_HW_HPP
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